These experiments, which involved using a -300 V DC bus, show that the gate voltage can be as high as -27 V, with a short-circuit withstand time ranging from 75 ms to 90 ms (see Figure 3 (a) and (b)). We have focused on evaluating the short circuit capability of the SiC p-MOSFET via measurements of drain current and gate voltage as a function of short circuit withstand time. The typical on-state, blocking characteristics for the fabricated SiC p-MOSFET. We are not too concerned with this high on-resistance, however, because we believe it could plummet by: adopting an advanced cell design, such as super-junction and turning to a trench gate structure and state-of-the-art fabrication technologies.įigure 2. A weakness of this transistor is its on-resistance, which is more than ten times that of the n-channel equivalent, due to the combination of a low hole mobility in the bulk and channel, the thick p+ substrate and the conventional gate oxidation process. With this process we form 3 mm by 3 mm p-MOSFET die.Įlectrical measurements on our p- MOSFETs reveal a typical threshold voltage of -5.32 V and a breakdown voltage in excess of -730 V (see Figure 2). After adding this, the steps to complete device fabrication are: the addition of a 50 nm-thick gate oxidation layer on the surface formation of the gate electrode, via the deposition and annealing of highly-doped polycrystalline silicon and the creation of source and drain electrodes with a metal process. Our p-MOSFET features a JFET region, formed by selective aluminum ion implantation that reduces resistance. On this surface we grow a 0.5 mm-thick n-channel region with doping concentration of 5à-10 15 cm -3. The bottom of the n- channel region is formed with selective implantation of nitrogen ions at a concentration of 4à-10 18 cm -3. On this we deposit a 5 mm-thick drift layer with a doping concentration of 1.6à-10 16 cm -3. The foundation for our p-MOSFET is a silicon-face, p- type 4H-SiC substrate with the thickness of 350 mm and resistivity of 2 Ωcm. It has a vertical structure (see Figure 1), and its fabrication involves n-channel implantation. Our device is a descendent of an implantation and epitaxial MOSFET developed by the National Institution of Advanced Industrial Science and Technology. The inset shows the wafer of the fabricated SiC p-MOSFET. The cross-section of the SiC p-MOSFET fabricated at Tsukuba University. This is highly undesirable, because it makes it very challenging to increase s witching frequency "“ and this is wanted, because it holds the key to smaller, lighter, more efficient inverters.įigure 1. However, addressing that problem introduces another: a relatively high total harmonic distortion in the output AC waveforms. To prevent this, engineers must ensure that the dead time, corresponding to the delay time of the gate driver circuit, is at least 1.0 ms. In these circuits, where p-type and n-type transistors are paired together, there is the potential for a short circuit to arise from the on-state of both devices. When they are deployed in conventional inverters, they are highly problematic. The weaknesses of silicon devices limit the efficiency of some circuits, and hold back the capability of others. These assets help SiC power devices to have the upper hand over silicon in many regards, including: a lower on-state resistance a higher maximum operating temperature a lower conduction loss and a smaller increase in chip temperature during operation, thanks to the high thermal conductivity. SiC is renowned for its wide band gap and large dielectric constant. BY JUNJIE AN, MASAKI NAMAI, MIKIKO TANABE, DAI OKAMOTO, HIROSHI YANO AND NORIYUKI IWAMURO FROM THE UNIVERSITY OF TSUKUBA
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